The present invention relates to improvements in a detector for data sampling, and is more specifically related to the timing recovery of a detector during data sampling.
Increasing density of data transmitted or stored reduces the cost of transmitting and storing the data and the time it takes to transmit and store data. Therefore, it has been a long term goal of the electronics industry to increase the density of data transmitted or stored. Many systems use run-length limited (RLL) coding and peak detection (PD) to achieve high reliability and high densities. A further increase in density can be achieved using more advanced techniques such as partial response (PR) signaling and maximum-likelihood (ML) sequence detectors such as Viterbi detectors, or a combination of the two.
Partial response (PR) signaling is a technique that enforces spectral properties and allows a controlled amount of intersymbol interference. ML sequence estimation, and particularly the Viterbi algorithm, improves the detection of symbol sequences in the presence of intersymbol interference. ML sequence estimation allows most PR schemes to perform practically in a system with errors caused by intersymbol interference.
PR signaling also allows a better handling of intersymbol interference and a more efficient utilization of the bandwidth of a given channel. Because the intersymbol interference is known to be present, the receiver can take it into account. PR signaling in communications allows transmissions at the Nyquist rate, and provides a favorable trade-off between error probability and the available spectrum. The PR systems described by the polynomials 1+D, 1xe2x88x92D, and 1xe2x88x92D2 are called duobinary, dicode, and class-IV, respectively, where D represents one bit cell delay and D2 represents 2 bit cell delays. D=e31 jxcfx89t, where xcfx89 is a frequency variable in radians per second and t is the sampling time interval in seconds. The PR4 magnitude response, 1xe2x88x92D2, emphasizes midband frequencies and results in a read channel with increased immunity to noise and distortion at both low and high frequencies.
Conventional disc drives are used to record and to retrieve information. As discs become more prevalent as the medium of choice for storing information in both computer and home entertainment equipment, disc drives likewise become more prevalent and important components of such electronic systems. PR and ML have been employed in communications signaling for many years, and have now been applied commercially within magnetic hard disk drives. PR4 is presently a preferred partial response system in disc drives, since there is a close correlation between the idealized PR4 spectrum, and the natural characteristics of a magnetic data write/read channel. Application of the Viterbi algorithm to PR4 data streams within a magnetic recording channel is known to improve detection of original symbol sequences in the presence of intersymbol interference and also to improve signal to noise ratio over comparable peak detection techniques.
EPR4 and EEPR4 are higher order PR detection schemes that further increase the density of data that can be stored and transmitted.
FIG. 1 shows a portion of a conventional detector 10, the detector 10 can be a PR4, EPR4, or an EEPR4 detector. The detector 10 has a slicer 20 that samples a data stream to obtain data samples xxe2x80x2(T).
The output of the slicer 20 is also connected to a phase error estimator 22, typically through an equalizer (not shown). The phase error estimator 22 is coupled to a D to A converter 24 whose output is provided to an oscillator 26, which generates the clock, clk(T), that clocks the slicer 20 to control the data sample rate. Each data sample xxe2x80x2(T) is passed to the phase error estimator 22 that determines the timing error for the sample xxe2x80x2(T) and outputs a signal that adjusts the clock frequency of the oscillator 26.
The output of the slicer 20 is also connected to a Viterbi detector. The slicer 20 outputs a sequence of data samples, which are input to the Viterbi detector 28 for analysis and detection to aid in obtaining the decoded data. The output of the Viterbi detector 28 provides the data stream to the system for further detection and analysis.
A problem with PR detectors 10 is that as the density increases or as the complexity of the detector increases the same amount of noise that was previously acceptable can cause false detection of the sample. A false detection can lead to a timing error that will cause the oscillator to adjust the clock frequency to an incorrect frequency. Clocking the slicer 20 at a frequency that does not match the data rate will cause the slicer 20 to sample the next data sample at the wrong time, which will lead to an incorrect data value and to an incorrect timing error for the next data sample, leading to the data value after that being sampled at the wrong time, and so on.
A detector for receiving data in accordance with the present invention includes a slicer, a sequence table of allowed sequences, and comparison circuitry. The slicer has an input terminal coupled to a read channel and an output terminal coupled to the first input terminal of the comparison circuitry. The sequence table has an output terminal coupled to the second input terminal of the comparison circuitry. The output terminal of the comparison circuitry is coupled to an input terminal of a phase error estimator.
In accordance with the method of operation of the circuit of the present invention, a data sample, a predetermined number of previous data samples and a predetermined number of subsequent data samples are obtained. Some of the data samples are used to form a sequence. The sequence is compared with the values in the sequence table to determine if it is an allowed sequence. If the sequence is an allowed sequence, the timing error of the detector is corrected based on the timing error of the data sample.
The novel features believed characteristic of the invention are set forth in the appended claims. The nature of the invention, however, as well as its features and advantages, may be understood more filly upon consideration of illustrative embodiments when read in conjunction with the accompanying drawings, wherein:
FIG. 1 is a block diagram of a portion of a conventional detector.
FIG. 2 is a block diagram of a portion of a detector according to an embodiment of the present invention.
FIG. 3 is a block diagram of one example of the comparison circuitry including the override circuitry.
FIG. 4 illustrates the timing correction vs. the phase error.
FIG. 5 is a block diagram of disc drive having a detector according to an embodiment of the present invention.
Appendix A is a program in Matlab for generating a sequence table for an EPR4 detector.
Appendix B shows all sequences that can occur in an EPR4 detection scheme.
Appendix C shows the values of the sequence table for an EPR4 detector.